AHB and AXI are both bus masters. Both these bus masters are a part of the AMBA (Advanced Microcontroller Bus Architecture) Bus. It is a target towards high Performance, Bandwidth, and frequency System Design.
Table of Contents
Both the bus masters are correlated though are different in many aspects and the differences are mentioned in this article below.
AHB vs AXI
The main difference between AHB and AXI is that AHB is a single-channel bus while on the other hand, AXI is not a single-channel bus. AXI is a multi-channel, read and write optimized bus. Also, AHB is a more usable protocol in ASIC Verification as well as for on-chip communication as compared to AXI.
Advanced High-performance Bus is a single channel Bus which is ARMs very popular protocol. It supports a Single outstanding transaction per bus master. The bus latencies of AHB start at 16 Byte transactions.
Some features of AHB are single-edge clock protocol, split transactions, large bus widths, locked transfers.
AXI is a multi-channel bus with 5 channels which are Read data channel, Write data channel, Read address channel, Write address channel and Write response channel. AXI supports multiple outstanding transactions.
The bus latencies of AXI start at 64 Byte transactions. Some features of AXI are QoS, Write strobes, full-duplex communication mode, etc.
Comparison Table Between AHB and AXI
|Parameters of Comparison||AHB||AXI|
|Full form||Advanced High-Performance Bus||Advanced extensible Interface|
|Channel||It is a single-channel bus.||It is a multi-channel bus.|
|Features||Early Burst termination, Locked Transfers||QoS, Write Data Interleaving, unaligned data transfer, byte invariance.|
|Address space assigned for a single slave||It is 1 KB for AHB.||It is 4 KB for AXI.|
|Burst Lengths||Burst Lengths for AHB are 1, 2, 6, 16. (except for INCR types)||Burst lengths are from 1-16 for AXI3, and from 1-256 for AXI4.|
What is AHB?
AHB stands for Advanced High-performance Bus. It is a single-channel bus which is also a shared bus having one address channel, a read data channel, and a write data channel.
Each of the bus masters in AHB connects to a single-channel shared bus. AHB has only two bus cycles in a simple transaction, an address phase, and a subsequent data phase. AHB has large bus widths.
In AHB, if a user is not able to meet the timing requirements then it does not support the pipeline which registers in its path.
And due to its inability to support pipeline registers insertion, it doesn’t enable higher frequency and instead it limits the maximum frequency for the design.
AHB does not support the QoS feature, write strobes, and the Exclusive supports. It supports locked transfers only. It has low power dissipation and limited throughput. Also, the burst lengths in AHB are fixed.
They are 1, 2, 6, 16 except for the case of INCR. In INCR, the burst can have any length although how long it will be is not shared. Also, it can have any length only till it doesn’t go across 4K.
AHB was introduced in AMBAversion 2 by the ARM limited company and it was a very popular protocol until the new version AXI wasn’t introduced.
What is AXI?
AXI stands for Advanced eXtensible Interface. It is a multi-channel bus designed for on-chip communication. It is a high-performance, high-frequency, Full-duplex mode communication interface.
There are 5 channels in AXI and each one is independent of the other.
The channels are Write address channel (AW), Write data channel (W), Read data channel aka R (Read response is sent with it as well), Read address channel (AR), and Write response channel (B).
Since AXI has 5 parallel channels running, many wires are used to lay the layout. A user can insert a pipeline register anywhere in the path of any one of the channels and because of it, AXI enables a higher frequency of operation.
Some of the features that AXI has are unaligned data transfer (using strobes), separate address/control, data phases, byte invariance, burst-based transactions with start address issued, QoS, out of order transaction completion, Write Data Interleaving, and atomic operations.
Indeed, AXI has additional Signalling mechanisms like AxRegion and AxUser.
There can be multiple data transfers for a single request in AXI which means it is a burst-based protocol. It makes it easier when a large amount of data have to be transferred from or to addresses of a specific pattern.
There are three types of bursts in AXI: FIXED, INCR, and WRAP. The length of these bursts is known from the start and they can be from 1-16 for AXI3 while 1-256 for AXI4.
Main Differences Between AHB and AXI
- AHB stands for Advanced High-performance Bus, which is a single channel bus. While AXI is a multi-channel bus and stands for Advanced eXtensible Interface.
- AHB does not support “out of order transaction” completion while AXI support “out of order transaction” completion.
- AHB has low power dissipation while AXI has high power dissipation.
- AHB Bus utilization is higher as compared to the AXI utilization as AXI uses 50% more power.
- Unaligned data transfer using strobe and byte invariance are some of the features which AHB wouldn’t support but AXI supports.
- AHB does not support write strobes while AXI supports it.
- AHB supports the locked transfer. While in the case of AXI, the AXI 3 supports the locked transfer while AXI4 doesn’t.
- AHB does not support the exclusive transfers while AXI supports them.
- The bus latencies of the AHB bus master start lower as compared to that of the AXIs.
Both AXI and AHB are part of the AMBA (Advanced Microcontroller Bus Architecture) Bus. Advanced High-Performance Bus aka AHB is a single channel bus in which each of the bus masters has to connect to a single-channel shared bus.
The AHB bus master doesn’t support the full-duplex mode.
AXI stands for Advanced extensible Interface, which is a multi-channel bus. It has 5 independent channels. Because of the multiple channels, AHB is a full-duplex mode of communication support bus master.
AXI supports features like unaligned data transfer (using strobe), QAS, Semaphore mode of Operation, byte invariance, and Write Data Interleaving. It is the third generation of AMBA.
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